Backside Etches of 4682 Release and Widen Pores

ByGreg Madejski

We have a wafer that did not clear 500 nm pores (400 nm thick silicon nitride, #4682). There are about 230 chips that could be useful if they were etched a little.

I used a SF6 based recipe (15 sccms O2, 30 sccms SF6, 10 sccms CHF3, 110/10 W FWD/REF power, 5e-5 torr base pressure, 30-50 mTorr etch pressure) for varying amounts of time (0, 50, 100, 160, 200 seconds) to see if we can get porous material.  The quoted etch rate is approximately 40 nm/min for silicon. The chamber was cleaned with an oxygen plasma, then seasoned with the etch recipe for 5 minutes. We etched the membranes from the trench side by placing the membranes facedown on a carrier wafer inside the etch chamber.

 

3600x Montage. Pores are regular throughout the etch process.

 

26500x +25deg Montage. The thickness of the membrane decreases and the sidewalls become rougher. Natively, the sidewall at 25 degrees is about 190 nm long. At 50 s of etch, the sidewall at 25 degrees is 180 nm long, at 200 s the sidewall at 25 degrees is 110 nm long.

 

The pore width increases as more material is removed. Natively, the pores are about 630 nm at the top and 420 nm at the bottom, which is then maximized at 200s of etch (735 nm at the top, 680 nm at the bottom). Also, the sidewalls become rougher.

 

Pores Widen as the etch time increases

 

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