SiOx (TEOS) microporous membrane liftoff from bare Si surface
Today, I finally demonstrated liftoff of microporous SiOx from a bare Si wafer. The sample is a 2 x 2 cm section of wafer 209A02, which has a 100 nm layer of TEOS SiOx that stress stabilizing anneal. The film was patterned with close-packed ø3 µm pores (6 µm pitch) using S1813 resist, G-line stepper photolith, RIE etch in Drytek Quad using SF6. The wafer was then stripped of resist in piranha followed by coating with 10 µm SU-8-3010. The SU-8 was patterned with our “standard” micro grid scaffold pattern (110 µm squares w/ 10 µm strut widths) using contact lithography. The mask we used is from Fineline in Colorado, and it is does not have very good resolution for these length scales. To strip the native oxide, I treated the sample for 15 s in the SF6 RIE. I placed a monitor sample in with this and determined that ~10 nm of the SiOx is also etched in this treatment, so the final SiOx sample for this test is 90 nm.
I placed the sample in the Xactix and ran it for the number of pules shown next to the figures, pausing in between to get optical microscope images. For comparison, the same size sample where the SiOx layer is on a 1 µm poly-Si layer on top of a 100 nm thermal oxide takes about 4-6 pulses to liftoff. Clearly, the lack of a vertical etch stop makes the process much less efficient (about 10-fold). However, it does in fact work: there’s no “clamping” issues with the membrane on the bare Si surface. In fact, when I finished the last wet of pulses, the membrane had already separated from the Si surface and was lying beside in on the platen in the etch chamber (see bottom left photo below). Likely. this is at least partly because the underlying silicon is becoming quite rough from the etch (see “Si surface” micrographs). I was able to lift the membrane with wafer tweezers and drag it onto a class slide with pieces of pdms.
Figure: All micrographs are 50x except for the one after 60 pulses is 10x. The number of XeF2 pulses are cumulative.