Wafers 620/621
Today I etched wafer 621, which is the pair to 620. While w620 has a relatively low pinhole density, w621 shows a much higher occurence of defects.
Since the front-end processing and thermal treatment was identical for these wafers, I believe that the variability lies in the etch process. Looking at the two wafers side-by-side, you can see that wafer 620 was underetched whereas wafer 621 was exposed to EDP for approximately 15 minutes longer. The longer exposure to EDP increases the liklihood that some chemical seeped through to the front of the wafer and was able to attack “weak spots” in the front oxide.
With our current etch cell geometry, the membranes do not etch through all at the same time. (That’s why some wafers are “missing” the outter most slits.) We believe this effect is due to a combination of uneven stirring and a temperature gradient across the wafer surface. The new etch cell will solve this problem by heating closer to the wafer surface and by using a wider stir bar.
Another source of etch variabilty may be caused by heating the EDP to an unstable temperature. Most of the literature suggests working at 100 – 118 C (boiling point). Our current set point is 115 C (hotter = faster). However, we’ve noticed that the sidewalls are rougher and the edges of the membrane are not as straight as they used to be. This could be a consequence of etching too quickly. For future etches, I’ll dial back on the temperature to see if there are any changes.
Has the temperature always been set at 115, or can you correlate the good membranes we’ve had with cooler etching? Also do you have a set time for the etch or is this variable depending on the wafer?
The etch time is variable depending on the exact thickness of the wafer, the temperature of EDP, and amount of stirring. I’ve always had to decide between underetching (decrease chances of EDP penetrating to the front) and overetching (clearing more outer membrane samples but increase chances of pinholes).