The permeability data is very different for films deposited at room temeperature and 400C.
The 400C deposited wafers have much higher permeability and more consistent.
w335 – RT
w336-RT
w338 -400C
w340 – 400C
Burst Pressures
This is a side view schematic of the experiments I’m setting up in Mike and Derek’s stir cell. The membrane separates two wells. In the well where the membrane is flush with the wafer I add 300uL 5nm gold in H2O. On the other side I add my buffer and a stir bar. Adding a…
Cindy Hartnett – professor of mechanical engineering at Louisville requested some pnc-Si chips after reading our PNAS paper. In requesting the material she mentioned … I’ve long been searching for a low-voltage way to drive some micro-actuators. Electrokinetic pumps looked good but until now the necessary voltage was far too high. About a month after…
Earlier in the week I retested the 100K microcons in our wet-wet EQ format. When I last ran them this way I calculated very little flow and very small permeability values. I noted that there was a rather large air pocket collecting on the underside of the membrane in the plastic support structure; most likely…
Last week I reported wafer 403 showed uniformity across all positions but had a huge amount of pinholes. Wafer 404 (TEOS process & thermal oxide base) was initially annealed at 1000 C and then annealed again at 1000 C for 5 minutes in the RTP. The second anneal helped with the sputtered oxide film quality…
Do not just send her an e-mail. The form found is found here
In my previous post, I mentioned that the EA treated chips showed decreasing contact angles after their storage in water in contrast to gel-pack or vacuum container. However the EA treatment was 4 days old, and I lacked adequate controls. So this time, I chose smaller time durations to understand if this phenomenon can be…
