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Negative Data for Nanofluidic Transistors, Dielectic ‘Flowers’, and an Interesting Gold Filtering Behavior
I’ve been trying for a year now to make a nanofluidic transistor – a nanomembrane with a thin layer of metal coated in dielectric that allows for the dynamic modulation of the sieving characteristics of the chip. Beginning with the last 14 chips from wafer #1081, I coated them in ~3 nm of Ti and…
Air Permeability (w 318, 319, 320, 307) and Updated Burst Pressures
There is some non-uniformity in air permeability based on the position but it is not very clear for wafers 318 and 319. The full wafer measurement in future will make this dependence more obvious.Permeability of w319 is much higher then of w318 (RTP 1000C and 900C) as expected from TEM images where w319 has higher…
Furnace annealing of free-standing NSN and OSO stacks (1)
ByJoe QiI have done some furnace annealing (FA) on free-standing NSN and OSO stacks in last two weeks after the RTP was down. I’ll show the results in the following two posts. In order to compare the annealing result, I chose both NSN and OSO stacks with the same structure of 30-25-30, which corresponding to 25nm…
Lower density fibroblasts on pnc-Si transwells
Last time I cultured fibroblasts on pnc-Si transwells, the cells got super-confluent over the membrane and made the analysis difficult. Basically, I wanted to see if fibroblasts formed vacuoles/2D structures over free-standing membranes. I thought the multi-layer cells could have choked off permeability and prevented the higher layers of cells from even sensing that they…
EO as a function of pore radius
ByJimFrom Jess’ manuscript … From Wikipedia … From Tom’s ACS nano paper … The Dagan equation (2) for flow through short pores used to predict flow through pnc-Si is given by: where r is the average pore radius, DP is the pressure drop across the membrane, l is the membrane thickness and m is the…
Update: 30/100/30 OSO, 30/75/30 & 30/100/30 NSN SEPCON
We are trying to reproduce the very small pores Joe created with 30/100/30 OSO and large pores created with 30/100/30 NSN using a SEPCON pattern. (Joe’s previous post.) We had a problem with several chips releasing from the center of the wafer prior to completely clearing all the features. In the future we will use…
