Initial ALD-ed chip sieving data

I made a size ladder of ALD-ed chips. The chips I began with were ~35 nm average pore size, and I applied 2, 5, 7, 10, and 12 nm of alumina using the ALD in UR nano. This does represent an incomplete data set – the 7 nm and 12 nm alumina chips I first tried broke, and I haven’t repeated those yet (although I have the chips to do so). Things pretty much make sense except for the 10 nm alumina chip used to filter 20 nm gold.

Below are some SEMs of the bare chips and ALD-ed chips. You’ll notice that there seems to be some variation in the film thickness that might explain the weirdness. The recipe I used was a standard one, with maybe particularly long soak times. But long soak times should result in more homogeneity, not less. Some of the chips did get blown over by the pump-down cycle of the ALD, an issue that we’ve dealt with before (although our previous solution doesn’t seem to work since UR nano rebuilt the vacuum pump), so that might have affected things. Visual inspection immediately after I made the chips did seem to show some chip to chip variation in alumina thickness (as determined by surface color) – I did not use 3 chips that seemed particularly different from the others.

Bare chip. SiN, ~35 nm average pore size, used to filter 30 nm gold:

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SiN chip with 2 nm alumina:

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SiN with 5 nm alumina:

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Here’s where I think it gets interesting. This is SiN with 7 nm alumina. This chip broke during a filtration of 20 nm gold, but had passed a quick test in the flow cell prior to that. 

 

Notice how there seems to be a film that obscures the pores in half the frame? Something similar is in the next one:

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10 nm of alumina:

 

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12 nm alumina: