Silicon Oxide Liftoff Update

I have been exploring the efficacy of different methods for removing the native oxide from the surface of the sacrificial silicon layer prior to liftoff etch with XeF2.  As a reminder, with liftoff of SiN membranes, one can simply dip the sample in BOE solution for a few seconds to strip the native oxide.  This is not desirable in the case of SiOx membrane liftoff, because the BOE will also etch away a significant amount of the oxide membrane.  Based on recommendations received from my earlier post, I tried two methods: vapor HF by suspending samples over a tank of 10:1 BOE and short RIE treatment in the Drytek Quad. I used samples from wafers where the microporous SiOx membrane (100 nm thick, ø3 µm, 6 µm pitch, close-packed pattern) was on a bare SI wafer and on a 1 µm poly-Si layer on top of a 100 nm thermal oxide.  The vapor HF was tried by placing samples (~2 x 2 cm) in a Teflon basket that was supported ~2 cm above the liquid surface of a 10:1 BOE tank for 30, 60, 90, and 120 s.  Samples were then placed in the Xactix and exposed to two pulses.  The samples with the poly-Si/thermal are convenient for this test because the dark blue color of the underlying thermal oxide provides excellent contrast for viewing the progress of the through-pore etch.  In general, this method does not appear to be very effective for stripping the native oxide at the times used so far.  Only in the case of the longest exposure times was any evidence of Si etching observed in the Xactix, and then it was not a uniform etch across the surface of the sample.  Probably, it would help to position the sample much closer to the liquid surface – more like a couple mm rather than ~2 cm.  I chose the 2 cm distance because this is the length scale of the tank’s lip, which makes it convenient to rest the edge of the basket on so that I get a consistent distance each time.  I’m sure I could come up with some fixture to allow a repeatable positioning much closer.  Second, I could simply go to longer exposure times, but again, I would want to come up with a fixture to ensure consistent positioning.

Next, I tried a brief RIE using the Drytek Quad.  I modified the standard SiOx etch recipe  (SF6 (50 sccm) and Ar (100 sccm) at 100 mTorr, RF plasma power 125 W) to run for only 15 seconds.  This time is probably considerably longer than what’s needed, and I’ll have to optimize it eventually, but I wanted to see if this would be effective in removing the native oxide while leaving an intact SiOx membrane that could be lifted off.  The results are promising for enabling effective LO etch.  I tried both types of samples.  I ran the one on bare Si first; after two pulse in the Xactix, it appeared that the etch has progressed about 1 µm in from the edges of the pores.  I exposed it to two additional pulses whereupon it appeared that the membrane had been etched free of the underlying wafer within the SU-8 grid windows.  It was very difficult to resolve whether the etch had progressed under the SU-8 struts due to the lack of contrast.  Thinking the sample was close to lifting off, I exposed the sample to 6 more pulses and attempted to lift it off by pressing a glass slide that has pdms strips bonded to it.  I found that the SiOx membrane only transfers the ~100 x 100 µm windows within the SU-8 grid.  Below is micrograph image of the SU-8 grid showing the progress of the etch.  Now that the etch had progressed a few µm under the SU-8 struts, it is easier to resolve the regions where the etch is not complete.

Figure 1: 50x image of 100 nm SiOx membrane on bare Si after 10 pulses of XeF2.  The membrane is etched free of the underlying Si surface within the SU-8 windows (~100 x 100 µm), and the etch has progressed several µm under the SU-8 struts.

Next, I wanted to see if the sample on the 1 µm poly-Si layer would liftoff, so I exposed it to 10 pulses in one run.  It was close to the time for the lab to close and I wanted to confirm that we could get clean liftoff of the SiOx membrane.  For reference, Josh Miller was able to get liftoff of SiN samples of this size with just 3 pulses.  The addition of the thermal oxide layer greatly improves the efficiency of the etch by limiting how deeply the XeF2 etched while etching across the ~15 µm distance under the SU-8 strut intersections.  After the 10 pulses, the sample was clearly lifting off from the sample.  I lifted the membrane with tweezers and attempted to lay it across pdms strips on a glass slide.  The membrane has a tendency to fold over on itself from static charge, so this process was not very successful as can be seen in the figure below.  Clearly, I need to work on the transfer process  Still, this is encouraging for SiOx liftoff.

Figure 2: Images of liftoff of a 100 nm thick microporous SiOx membrane from thermal oxide covered wafer.

I next want to test the process with  bare wafer samples again to see if I can get liftoff.  Clearly, it will take a much longer etch process given the lack of an etch stop.  I also need to optimize the RIE etch for time and quantify how much of the SiOx membrane is etched during this process.  I ultimately would prefer to use the vapor HF process because the RIE will attack the SU-8 grid and could kick up hydrocarbon contamination all over the surface.